This article is mainly about the related introduction of nor flash, and focuses on the detailed description of the power-on method and principle application of nor flash.
nor flashNor flash is one of the two main non-volatile flash memory technologies currently on the market. Intel first developed the NOR Flash technology in 1988, which completely changed the original EPROM (Erasable Programmable Read-Only-Memory) and EEPROM (Electrically Erasable Programmable Read-Only Memory). The situation that dominates the world. Then, in 1989, Toshiba announced the NAND Flash structure, emphasizing lower cost per bit, higher performance, and easy upgrade through the interface like a disk. The characteristic of NOR Flash is the execution in the chip (XIP, eXecute In Place), so that the application program can run directly in the Flash flash memory without reading the code into the system RAM. The transmission efficiency of NOR is very high, and it is very cost-effective in the small capacity of 1~4MB, but the very low writing and erasing speed greatly affects its performance. The structure of NAND can provide extremely high cell density, can reach high storage density, and the speed of writing and erasing is also very fast. The difficulty in applying NAND is that the management of Flash requires a special system interface. Generally, the reading speed of NOR is slightly faster than that of NAND, and the writing speed of NAND is much faster than NOR. These conditions should be considered in the design.
Flash flash memory is a non-volatile memory, which can erase and reprogram memory cell blocks called blocks. The write operation of any flash device can only be performed in empty or erased cells, so in most cases, the erase must be performed before the write operation. It is very simple for NAND devices to perform an erase operation, while NOR requires that all bits in the target block be written as 0 before erasing.
How to start norflashIf an electronic product has no electricity, it is no different from a waste product. It is electricity that gives them life, but the program is their soul.
When I was young, I was always curious, why do all the rigid electronic products work after power-on? Why can a small chip be able to run the program we write? How can a development board run from the moment it is powered on to the entire operating system? These things have been troubled for a long time, and now I have slowly figured out some of these principles after referring to a lot of information.
Most of the electronic products we come into contact with are designed using digital circuits. The essence of digital circuits is two numbers: 0 and 1. The ever-changing combination of these two numbers creates the colorfulness of the computer world, whether it is cpu or memory. Or other peripherals are recorded, interacted and calculated through the changes of 0 and 1. How does the hardware operate these two numbers and how these two numbers control the hardware work? I won’t discuss them here. They are all knowledge about diodes, triodes, NAND gates, signal amplification, sampling, coding, etc. A fully functional chip, after power-on, they analyze the process of completing various operations through electrical signals. If you have played with single-chip microcomputers, you should know that a cpu plus a power supply and an external crystal oscillator can be used to make a minimal system. The single-chip microcomputer can run in his poor 64k or 128k memory. These simple Although the control chip has its existence value, it cannot meet the increasingly complex computing needs, so it needs faster computing speed and larger running memory, so we will use more complex processors, such as mips, arm, etc. The following will use the arm s3c2440 processor to analyze the process of power-on startup.
As an embedded product, its diversity makes it more playable and easier to adapt to different needs. It is not like our PC boot method is relatively simple (ROM boot), arm boot method has to start from norfalsh, nandflash boot, SD card boot and UBS boot, etc., but their boot principles are similar.
Before starting, clarify a few concepts:
SDRAM (Synchronous Dynamic Random Access Memory): Synchronous Dynamic Random Access Memory. Synchronization means that the memory work requires a step clock, and the transmission of internal commands and data transmission are based on it; dynamic means that the storage array needs to be constantly refreshed. Ensure that the data is not lost; random means that the data is not stored linearly in sequence, but read and written from the specified address. Simply put, it is the external memory used by the cpu, which is what we often call the memory bar.
SRAM is the abbreviation of English Static RAM. It is a kind of memory with static access function. It can save the data stored in it without refreshing the circuit. It is faster than SDRAM and is generally used as a high-speed buffer memory (Cache).
norflash: Non-volatile flash memory, is an external storage medium, executed in chip (XIP, eXecute In Place), so that the application can run directly in the flash flash memory, no need to read the code into the system RAM, because it has an address Bus, cpu can directly fetch instructions from norflash, and run programs directly from FLASH, but the process is complicated, the price is more expensive, the capacity is small (1~4M), and the transmission efficiency of NOR is very high.
nandflash: It is also a kind of non-volatile flash memory (not lost after power failure), but although it has a data bus, it does not have an address bus, so the cpu cannot directly fetch instructions from nandflash. Because it is cheap, it is often used Store a large amount of data, similar to the hard disk we often say.
The following will analyze the two methods of nandflash startup and norflash startup (arm s3c2440), and other startup methods will be analyzed in the uboot code section.
1. Nandflash starts
First, a correct bootload must be programmed to the lowest position of nandflash, that is, start programming from 0x000. When we choose to start the development board from nandflash, the development board will start the circuit structure connected to nandflash. When the development board is powered on, the Nand Flash controller will automatically move the first 4K data on the Nand Flash to the CPU. In the internal RAM (SRAM-cache), this internal RAM is usually called a stepping stone. At the same time, the on-chip SRAM is mapped to the nGCS0 chip select space (ie 0x00000000), and the CPU starts from the 0x00000000 location of the internal RAM (execute) , This process does not require program intervention.
This process is stage1 of the startup process. It copies the first 4 contents of nandflash to stepping stone, and then starts execution from the first instruction of stepping stone. The instructions in the 4k content will complete the following actions:
1. Hardware device initialization
2. Load the U-Boot second stage code to the SDRAM space
3. Set up the stack
4. Jump to the second stage stage2 code entry
From the figure below, we can see the memory mapping relationship after the board is reset. The following points can be seen from the figure:
1. At the beginning, bank0~bank5 can only be mapped to SROM, while bank6 and bank7 can be connected to SDRM, and each bank can be connected to a maximum of 128M SDRM, so it is determined that the maximum external SDRAM of S3C2440 is 256M;
2. From the figure we can see that the starting address of bank6 is 0x3000_0000, so when we perform the second action of stage1 (loading the U-Boot second stage code to the SDRAM space), we need to put the uboot code to 0x3000_000~ In the interval of 0x4000_0000 (in SDRAM), stage2 can be executed normally from SDRAM;
3. When booting from nandflash is not selected, the starting address of Boot internal SRAM (4k) is 0x4000_0000. When booting from nandflash is selected, the starting address of Boot internal SRAM (4k) is 0x00, because our development board has no external connection SROM, so bank1~bank5 are free, and the location of bank0 will be replaced by Boot internal SRAM (4k), that is to say, the first 4k of bank0 is the stepping stone. After the board is powered on, it is in the startup mode of nandflash Next, S3C2440 will complete the address mapping in the following figure on the hardware, and automatically copy the first 4k in nandflash to the stepping stone, and get the first instruction from the starting address (0x00) of the stepping stone and execute it.
After the above analysis, we can merge the above two figures into the following figure:
I mentioned the first code movement during the startup process of nandflash, and the second code movement will be analyzed below. This 4k code will first set the cpu operating mode, turn off the watchdog, set the clock, turn off the interrupt, initialize the memory, initialize nandflash, and set Stack, then transport the entire bootload to SDRAM and jump to SDRAM for execution.
The basic process is shown in the figure below:
The execution process of the 4k code will be explained in detail later, and in the new uboot-2015, the 4k code is completed by uboot_spl.bin, the following will be based on uboot-2015.10 to list the entire uboot from power-on to booting the kernel Overview of the process:
Two, norflash start
In fact, if you understand the startup method of nandflash, the startup of norflash is much easier to understand. The first thing you need to know is that norflash can execute code (XIP) on the chip, that is, we only need to flash the bootload to the beginning of norflash Address, when the development board is powered on, you can know from the memory map that the nor flash will be mapped to the address 0x00000000 (that is, nGCS0, there is no need for the on-chip SRAM to assist here, so the starting address of the on-chip SRAM is still 0x40000000, Will not change), and then the cpu starts from 0x00000000 (that is, executed in Norfalsh) the entire uboot, until the boot kernel starts.
Starting from norflash can save a lot of trouble, not only that, the bare metal program we write by ourselves needs to be debugged, and it is usually burned directly into norflash, because as long as we put the compiled executable file at the beginning of norflash, the development board After the power is turned on, the instructions will be fetched and executed from the first instruction of norflash, and the debugging of the bare metal program that we write later is carried out in this way.
Although starting from norflash is very convenient from a development point of view (in fact, it is not much convenient), it increases its cost from a product point of view. After all, norflash is relatively expensive. We clearly only need one piece of nandflash to start the entire development board. Now, there is no need to add a piece of norflash to the product. As long as the code is changed, it can save a lot of cost, why not do it. And nandflash is indispensable to the product, because the kernel and file system are stored later, at least tens of megabytes of space are needed, and it is not practical to use norflash to store.
You may be wondering, can you just use norflash instead of nandflash and SDRAM. After all, norflash can store and run programs. It is theoretically possible, but understand their market price and operating speed. And the working principle, you should know the answer.
ConclusionThis is the end of the related introduction about nor flash. Please correct me if there are any deficiencies.
Related reading recommendations: Detailed explanation of the difference between NAND flash and NOR flash
Related reading recommendations: a detailed analysis of the difference between NorFlash and NandFlash
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