This article is mainly about the introduction of amd's second-level cache, discussing the size of the second-level cache and its selection range, and hope that this article will give you a deeper understanding of the second-level cache.
Secondary cacheThe working principle of the cache is that when the CPU wants to read a piece of data, it first looks it up in the cache, if it finds it, it reads it immediately and sends it to the CPU for processing; if it doesn’t find it, it reads it from the memory and sends it to it at a relatively slow speed. CPU processing, and at the same time transfer the data block where this data is located into the cache, so that the entire block of data can be read from the cache in the future, without having to call the memory.
It is this read mechanism that makes the CPU read cache hit rate very high (most CPUs can reach about 90%), which means that 90% of the data that the CPU will read next time are in the cache, only about 10% Need to read from memory. This greatly saves the time for the CPU to directly read the memory, and also makes the CPU basically no need to wait when reading data. In general, the order in which the CPU reads data is cached first and then memory. The earliest CPU cache is a whole, and the capacity is very low, Intel has classified the cache since the Pentium era. At that time, the cache integrated in the CPU core was not enough to meet the needs of the CPU, and the limitations on the manufacturing process could not greatly increase the capacity of the cache. Therefore, there is a cache integrated on the same circuit board or motherboard as the CPU. At this time, the cache integrated with the CPU core is called the first level cache, and the external one is called the second level cache. The first level cache is also divided into data cache (Data Cache, D-Cache) and instruction cache (InstrucTIon Cache, I-Cache). The two are respectively used to store data and execute instructions for these data, and both can be accessed by the CPU at the same time, reducing conflicts caused by contention for Cache, and improving processor performance.
How much better amd secondary cacheAMD processor processor data uses continuous processing, the processors process one by one, not random. Almost every data comes directly from L2, because the size of L2 is limited. When the size of a single data exceeds L2, AMD only needs to access the memory or when the data associated with the previous data is in the memory. RAM.
For example: AMD's processing method is like moving things from a warehouse, L2 is a small warehouse, memory is a large warehouse, and moving things from the small warehouse L2 is the fastest. The processor accesses data directly from the small warehouse every time, but occasionally In some cases, the things to be moved were too big to fit in the small warehouse, so they had to be moved from the large warehouse.
Due to AMD's continuous processing method, the demand for L2 only needs to look at the size of a single data. When L2 can satisfy most single data, there is no need to improve L2.
In the single data to be processed by the cpu, 0-64kb accounted for 50%, 64-128kb accounted for 25%, 128-256kb accounted for 15%, 256-512 accounted for 8%, and the remaining 2% was larger than 512kb.
When 512kb can meet most of the requirements, there is no need to increase a lot of cost in order to improve the small performance, so 512k is enough.
When Intel designed the processor, it adopts the random processing mode, which means that when the Intel processor needs to process a data, it randomly selects a data to process. When the data is in L2, it is directly from Reading in L2, when not in L2, you need to access the memory. It is necessary to know that L2 is much faster than memory. Therefore, Intel needs to increase the capacity of L2 to improve the overall capacity of the cpu.
for example:
Intel’s processor is like a person throwing a flying beacon, the red heart is L2, and other places are memory, and the flying beacon is randomly casted, and the probability of casting to each place is the same. If you want to increase the probability of hitting the high-speed heart area, the most direct and good way is to increase the area of ​​the heart, which is to increase L2. Therefore, Intel's processor is particularly large L2.
The scope of choice for amd secondary cacheAMD and Intel: The huge differences are due to different designs
When it comes to the gap in the capacity of the secondary cache, we have to start with the understanding of the two major CPU giants on the primary cache. Yes, you read that right, it is the "level one cache" whose usual exposure rate is far lower than that of the second level cache! It is the "culprit" that caused the huge differences mentioned above.
In today’s CPUs, Intel’s understanding of the primary cache is "data code instruction tracking cache", that is, what is stored in the primary cache is actually the address of the data and instructions in the secondary cache, not a copy of these data and instructions. . The capacity of the second-level cache affects the performance of the Intel CPU to a considerable extent.
In contrast, AMD's positioning of the first-level cache is "real data read-write cache", that is, part of the data in the second-level cache must be moved to the first-level cache under certain rules.
Not only is there a difference in the way the first level cache works, but AMD’s CPU also has an advantage in the size of the first level cache. Take AMDAthlon64X26000+AM2 (box) as an example. The two cores are equipped with 64KB data cache and 64KB instruction high speed. Cache. The slightly more expensive IntelCore2DuoE6320 (three-year box), each of the two cores is equipped with 32KB data cache and 32KB instruction cache.
Of course, the above is just the main reason for the huge difference in the second-level cache of Intel's AMD CPU. In fact, whether the CPU is "sensitive" to the L2 cache capacity is also affected by many aspects such as the memory controller, pipeline length, frequency, bus architecture, and instruction set. In a multi-core CPU, it is also related to the data exchange between each physical core.
In a multi-core CPU, the utilization efficiency of the secondary cache is high or low. To put it simply, Intel's new generation of Core architecture L2 cache is the best, followed by AMD's AthlonX2 series, and the older PenTIumD (PenTIumEE) series is the worst.
In a few years, the secondary cache has grown from a small 64KB to 8MB in one fell swoop, a full 128 times! Does the increasing size of the second-level cache really result in the same "rapid advancement" in CPU performance? Or is it just a digital game played by Intel and AMD?
In fact, the impact of the L2 cache capacity on performance is gradually weakening. When the L2 cache never grows to 128KB, the performance improvement brought by it may rise straight. But when it grows from 2MB to 4MB, users may not even feel the performance improvement. This is because in the current process of data processing by the CPU, a cache of less than 128KB is needed almost all the time, but rarely (about 2%) when a cache of more than 1MB is needed. Therefore, although the second-level cache is getting bigger and bigger, the actual impact on CPU performance is getting smaller and smaller. Like the two CPUs at the beginning of the article, the huge difference in the second-level cache will not ultimately manifest itself in the CPU speed. Therefore, it is completely unnecessary to blindly pursue the high capacity of the secondary cache, just enough.
Utilization of secondary cacheOverview
The CPU finds useful data in the cache is called a hit. When there is no data needed by the CPU in the cache (called a miss at this time), the CPU accesses the memory. In theory, in a CPU with a second-level cache, the hit rate for reading the first-level cache is 80%. That is to say, the useful data found in the CPU's first-level cache accounts for 80% of the total data, and the remaining 20% ​​is read from the second-level cache. Due to the inability to accurately predict the data to be executed, the hit rate of reading the second-level cache is also about 80% (reading useful data from the second-level cache accounts for 16% of the total data). Then there is still data that has to be called from memory, but this is already a fairly small percentage. In higher-end CPUs, there will also be a third-level cache, which is designed for data that misses after reading the second-level cache—a cache. In a CPU with a third-level cache, only about 5% of the data needs to be retrieved. Called in memory, which further improves the efficiency of the CPU.
In order to ensure a high hit rate during CPU access, the content in the cache should be replaced according to a certain algorithm. One of the more commonly used algorithms is the "Least Recently Used Algorithm" (LRU algorithm), which eliminates the least visited rows within a fixed period of time. Therefore, it is necessary to set a counter for each row. The LRU algorithm clears the counter of the hit row and adds 1 to the counters of the other rows. When replacement is needed, the data row with the largest row counter count is eliminated. This is an efficient and scientific algorithm. Its counter clearing process can eliminate some data that is no longer needed after frequent calls from the cache and improve the utilization of the cache.
Processor cache
The so-called processor cache usually refers to the secondary cache, or external cache. The cache memory is a small but high-speed memory located between the CPU and the main memory DRAM (Dynamic RAM), usually composed of SRAM (static random access memory). Used to store data that is frequently used by the CPU, so that the CPU does not have to rely on slower DRAM (Dynamic Random Access Memory). L2 cache has always been a very fast and expensive type of memory, called SRAM (Static RAM), SRAM (StaTIc RAM) is the English abbreviation for static memory. Since SRAM uses the same semiconductor process as the CPU, compared with dynamic memory DRAM, SRAM has a faster access speed, but is larger in size and expensive.
Brand difference
In fact, Intel and AMD processors differ in the logical structure design of the first-level cache, so the impact of the second-level cache on the CPU performance is also different. Because 80% of the data (including instructions) read by the CPU comes from the first-level cache, the logical structure of the first-level cache determines the impact of the CPU's second-level cache capacity on the performance of the CPU. The first level data cache of Intel's Pentium 4 and Celeron series processors is called "data code instruction trace (read and write) cache"; the first level data cache of AMD's Athlon 64/Athlon XP/Sempron/Duron series processors is called "Real data read and write cache".
ConclusionThat's it for the related introduction of amd secondary cache. Please correct me if there are any deficiencies.
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