Three digit display capacitance test chart circuit diagram

Test - lowercase jpg
Kaixin micro test
Test probe P100-M3

description:

The majority of electronic enthusiasts have this experience. Although the medium and high-end digital multimeters have capacitance test gears, the measurement range is generally only 1pF~20μF, which often cannot meet the needs of users, which brings inconvenience to capacitance measurement. The three-digit display capacitance test table introduced by this circuit adopts four integrated circuits. The circuit is simple, easy to manufacture, digital display is intuitive, and the precision is high. The measurement range can reach 1nF~104μF. Especially suitable for lovers and electrical maintenance personnel to make and use.

Circuit working principle

The circuit principle is shown in the figure.

Three digit display capacitance test chart circuit diagram
Three digit display capacitance test chart circuit diagram

The capacitance meter circuit is composed of a reference pulse generator, a capacitance capacity time converter to be tested, a gate controller, a decoder, and a display.

The capacitance capacity time converter to be tested converts the capacity of the measured capacitance into a one-shot time td proportional to its capacity value. The reference pulse generator produces a standard cycle count pulse. The turn-on time of the gate controller is the one-shot time td. During the td time, the cycle count pulse is sent to the back counter through the gate, and the decoder drives the display to display the value. The period T of the counting pulse multiplied by the count value N displayed by the display is the one-shot time td. Since td is proportional to the capacity of the capacitor to be measured, the capacity of the capacitor to be measured is also known.

In Figure 2, the integrated circuit IC1B resistors R7~R9 and capacitor C3 form the reference pulse generator (essentially an unstabilized multivibrator), and the output pulse signal period T is related to R7~R9 and C3, fixed at C3. In the case of different selections of R7, R8, and R9 by the range switch K1b, three pulse signals with periods of 11 μs, 1.1 ms, and 11 ms are obtained.

IC1A, IC2, R1~R6, buttons AN and C1 form the time capacity converter (substantially a one-shot circuit) of the capacitor to be tested. Pressing AN once, IC10B's pin 10 generates a negative narrow pulse trigger IC1A, and its 5 pin outputs a single high level signal. R3~R6 and the capacitor CX to be tested are single-stability components, and the one-shot time td=1.1 (R3~R6)CX. IC4, IC2C, C5, C6, R10 form the gate controller and counter. IC4 is CD4553. Its 12-pin is the count pulse input terminal, and the 10-pin is the count enable terminal. CD4553 performs counting at low potential, and 13-pin is count clear. End, the rising edge is valid. When AN is pressed, IC4's 13 pin gets a rising pulse, the counter is cleared, and IC2C's 4 pin outputs a one-shot low level signal to IC4's pin 10, so IC4 counts the reference input from its 12-pin. The pulse is counted. When the one-shot time is over, IC4's pin 10 goes high, IC4 stops counting, and finally IC4 uses the time-sharing mode to count the bit, tens, and hundred of the count result from its 9-pin, 7-pin, and 6-bit. The foot and the 5-pin loop output the corresponding BCD code.

IC3 constitutes the decoder driver, which translates the BCD code sent from IC4 into a decimal digital pen segment code, and directly drives the seven-segment digital tube after R11~R17 current limit. The 15th, 1st, and 2nd pins of the integrated circuit CD4553 are digital selection outputs. The pulses are sent to the bases of the transistors T1~T3 through R18~R20 to make them turn on. The two parts are matched to complete the three-digit decimal. Digital Display.

The role of C7 is to generate a rising pulse on R10 when the power is turned on, and the counter is automatically cleared.

Second, the component selection

In the circuit, IC1 selects NE556; IC2 selects CD4001; IC3 selects CD4543; IC4 selects CD4553. The seven-segment digital tube can be used with a three-word common cathode digital tube. 850 (or other PNP type triode) is used for T1~T3. C1 should not be larger than 0.01μF, and C3 uses small metallization capacitors. R3~R9 use 1/8W metal film resistor. There are no special requirements for other components, and you can select them according to the circuit labeling.

Third, production and debugging methods

After the whole circuit is installed, it can be installed in a plastic box, and the digital tube and the range switch are mounted on the panel. In the production and debugging, the key is to call out three standard pulse signals of 11μs, 1.1ms and 11ms. It is necessary to adjust the resistance of three resistors such as R7, R8 and R9 by using an oscilloscope during debugging. These three pulse signals are conveniently obtained. The resistance values ​​of R7, R8 and R9 in the circuit are experimental data for reference only. The rest of the circuit does not need to be debugged. As long as the good device is selected, the installation is correct, and the corresponding override is marked at the range switch, a practical, accurate and reliable digital capacitance meter can be obtained.

Fourth, the method of use

When testing the capacitor, multiply the count result by the multiplier of the range to determine the capacity of the capacitor under test. For example, when the reference pulse period is 1.1ms and the timing resistance is 10K, the range multiplier is 0.1μF. If a capacitor with a nominal capacity of 4.7μF is measured, the result is 49 when the AN is pressed. The capacity of the capacitor is 49 x 0.1 μF = 4.9 μF.

It should be noted that when using the 1pF~999pF range, the measurement result minus the distributed capacitance value is the accurate value of the measured capacitance due to the influence of the distributed capacitance. The range distribution capacitance value of the capacitance meter can be measured in this way, and the range is set in the range of 1pF~999pF. When the measured capacitance is not connected, the AN button is pressed, and the measured result is the distributed capacitance value of the block. The value is generally about 10 pF after experimentation.

The schedule lists the compositional relationships of the various ranges.

Schedule

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