The display panel made of LCD liquid crystal display is widely used in military equipment. This design uses Spartan-3E FPGA as hardware. The 2&TImes; 16-character LCD embeds a Sitronix ST7066U graphics controller to realize the characters or Chinese characters of the LCD display. Full screen display, full screen mobile display and single character moving display on the screen, all functions are realized in VHDL language, in line with LCD display requirements, to achieve various display effects.
Due to its small size, light weight, and low power consumption, LCD liquid crystal displays are widely used, such as display panels on airplanes, tanks, and ships, which can reduce the space occupied by the original CRT display, reduce the weight of the device, and enhance maneuverability.
This design uses a character LCD embedded with the Si.tronix ST7066U graphics controller on the Spartan-3E development board to achieve: (1) display of a single character at any position and full-screen display of characters and full-screen mobile display; (2) Display of custom characters (Chinese characters) and full screen movement display of single characters. Among them, the graphics controller [1] is responsible for receiving control commands and data and transmitting them to the LCD display.
1 Sitronix ST7066U graphics controller
The controller has three internal storage spaces, DD RAM, CGROM, and CG RAM, which should be initialized before sending data.
(1) DD RAM (display data RAM)
Store character encoding. Physically, DD RAM has a total of 80 character positions, each line has 40 characters, but only 16 can be displayed, and the remaining 24 are not displayed. Before reading or writing, the address counter needs to be initialized. The address counter can be kept constant or automatically incremented or decremented by one after reading or writing.
(2) CG ROM (character generator ROM)
A font bitmap containing each predetermined character.
(3) CG RAM (character generator RAM)
Contains 8-bit custom character bitmaps. Each custom character bit consists of 5 points in an 8-line bitmap. The usage is the same as DD RAM.
1.1 Interface signal with FPGA
The interface signals of LCD and FPGA [2] are: (1) enable signal LCD_E; (2) register select signal LCD_RS; (3) read/write control signal LCD_RW; (4) 4 LCD data lines and StrataFlash data line SF_D "11:8" reuse.
1.2 Timing Analysis
The data value of SF_D "11:8", LCD_RS, LCD_RW must be established and stabilized for at least 40 ns before LCD_E goes high, and LCD_E remains high for at least 230 ns. In many applications, LCD_RW is always low because data is not normally read from the display.
As shown in Figure 1, the data is transmitted in 8-bit form, divided into high 4 bits and low 4 bits. The first 4 bits are transmitted first and then the lower 4 bits are transmitted, and the interval is at least 1 us. An 8-bit write operation must be at least 40 us before the next communication, and the delay must be increased to 1.64 ms after the clear command.
Figure 1 Character LCD interface timing diagram
2 data display design
2.1 Flow chart
As shown in Figure 2, the LCD data display includes power-on initialization, configuration display, and write data to the display. The initial address should be set before writing data.
Figure 2 LCD display flow chart
The development board crystal is 50 MHz.
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