With the rapid development of electronic technology, the types of memory are increasingly numerous, and each type of memory has its own unique operation timing. In order to improve the test efficiency of the memory chip, a test system of a multi-function memory chip has emerged. This paper proposes a hardware design and implementation of a test system for a multi-function memory chip, and performs detailed junction circuit design for various memory chips (SRAM, MRAM, NOR FALSH, NAND FLASH, EEPROM, etc.) with various data bits. (How to mount to the NIOSII bus), finally solved the same platform test solution for multiple memories with different data bit widths, and designed the hardware implementation methods of each junction in detail.
Design principle
According to the above-mentioned various memory read and write timing access characteristics, the design scheme appropriately adjusts the external bus timing of the NIOS II through the flexible programming characteristics of the FPGA, and finally realizes the accurate operation of the NIOSII-based external bus to access various memory read and write timings. See Figure 2-1. Customize a bus interface -ABUS that can mount all memory chips through the FPGA, as shown in Table 1. Moreover, various tested test memory chips can be automatically identified on the same interface, which are distinguished by a category input signal (CLAS), each of which corresponds to a unique operational sequence. The following are the interface connections and signal descriptions of several memory chips. Other memory chips can be mounted to the ABUS bus with a similar connection and the test is finally completed.
Figure 2â€1 NIOSII bus mounts various types of memory chip connection diagram
Table 1: ABUS interface signal description table
40-bit NAND FLASH connection design
As shown in Figure 2-2, 40-bit NAND FLASH and NIOSII are bridged by ABUS (FPGA) to completely convert the timing of the external bus to the operational timing of NAND FLASH. The 40-bit NAND FLASH chip is composed of five independent 8-bit NAND FLASH chips. The external IO ports of the five 8-bit devices are spliced ​​into 40-bit external IO ports, and the respective control lines (NCLE, NALE, NRE, NWE) are connected together to form a set of control lines (NCLE, NALE, NRE, NWE). The chip selects are independently derived into NCS0-NCS9, and the busy signals are independently derived as R/B0-R/B9.
As shown in Table 2, the connection relationship between 40-bit NAND FLASH and ABUS is detailed.
Figure 2â€2 ABUS and 40-bit NAND FLASH interface diagram
Table 2, 40-bit NAND FLASH interface connection table
8-bit NAND FLASH connected to NIOSII
8-bit NAND FLASH is a multi-chip 8-bit NAND FLSAH chip, and each chip's external bus and control lines (NALE, CLE, NEW, NRE) are connected. The chip select and busy signals NCS0-NCS9 and NRB0-NRB9 of each chip are respectively taken out. The logic of the FPGA can be used to modify the bus read and write timing of NIOSII to accurately operate the large-capacity 8-bit NAND FLASH memory module. Achieve NIOSII to ABUS, ABUS to 8-bit NAND FLASH connection. As shown in Figure 2-3.
Table 3 details the connection between 8-bit NAND FLASH and ABUS.
Figure 2â€3 ABUS is connected to 8-bit large-capacity NAND FALSH
Table 3, 8-bit NAND FLASH interface connection table
40-bit SRAM connected to NIOSII
The 40-bit SRM module is connected to the NIOSII via ABUS for correct timing read and write operations. During the test, only 8 bits were tested at a time, and all the space tests were completed in 5 times. See Figure 2-4. Table 4 is a detailed description of the signal connections.
Figure 2â€4 ABUS and 40-bit SRAM connection
Table 4, 40-bit SRAM interface connection table
8-bit SRAM connected to NIOSII
The 8-bit SRM module is connected to the NIOSII via ABUS (FPGA) for correct timing read and write operations. As shown in Figure 2-5. Table 5 is a description of the signal connection.
Figure 2â€5 ABUS and 8-bit SRAM connection
Table 5, 8-bit SRAM interface connection table
Hardware circuit design
When testing NAND FLASH, the test time can be as long as ten hours. In order to improve test efficiency and increase test speed, this design consists of two identical and independent hardware systems. Up to 2 NAND FLASH devices can be tested simultaneously. Each hardware system consists of a microprocessor (NIOSII) plus a large-capacity FPGA and a memory test expansion interface (ABUS interface). See Figure 3-1. The RS232 communication interface realizes the data exchange between the test system and the host computer, and completes the human-computer interaction operation. The power system generates a variety of suitable voltages to meet the power supply of each chip.
Figure 3â€1 Hardware Block Diagram
Processor module circuit
The processor module circuit is composed of NIOSII soft core (CPU) embedded in FPGA, two-way RS232 communication, one FLASH core and one SRAM chip. The CPU is the core manager of the whole system. It is responsible for the read and write tests of various memory chips, and is responsible for communicating with the host computer to realize human-computer interaction. Communication is done by one of the RS232 circuits, and another RS232 circuit is used to implement system debugging and software curing. The FLASH chip is used to store program code and important data. After the CPU is powered on, the SRAM chip loads the FLASH program through the CPU, and finally provides a fast running environment for the CPU program code.
FPGA-based ABUS interface module
The ABUS interface module consists of an FPGA chip, a configuration FLASH, and a data storage EEPROM chip. ABUS needs to realize the interface between the external bus of NIOSII and various memory modules. Each specific memory has a specific timing logic, and each timing logic can be realized by the hardware code (IP core) of the FPGA. Each memory module will give the ABUS interface a fixed class signal CLAS during testing. The ABUS interface identifies various SIP memory modules according to this class signal, and finally switches out the correct timing logic corresponding to the specific product to complete the NIOSII through the external bus. To read and write tests on the memory chip. The FLASH is configured to implement the loading of the hardware program and the power-down data protection of the FPGA during power-on. The EEPROM is used to store some important system parameters.
SIP memory test extension interface
The memory test expansion interface consists of two rows of double row seats on the hardware. A total of 120 pins. The ABUS interface is connected to the test expansion interface: 40 pins are connected to bidirectional data or I/O lines, 8 pins are connected to 8 signal input control lines, and 16 pins are connected to 16 chip select signal output lines. 5 pins are connected to 5 class input signals, 16 pins are connected to 16 state input signal lines, and 27 pins are connected to 27 address lines. Other pins can be assigned to power and ground, as well as signal indications.
Design of ABUS interface IP core
Each SIP memory corresponds to a specific ABUS interface IP core for proper timing read and write operations. This IP core has a unified interface convention, which consists of two fixed interfaces. The external bus interface is connected to NIOSII, and its operation is implemented according to the external bus timing specification of NIOSII. The other interface is mentioned above. The ABUS interface is responsible for converting the external bus read and write timing of the NIOS II to the timing of the corresponding memory chip when the corresponding CLAS signal is valid. The job of the IP core is to complete the conversion of these read and write operations. Table 5 is the category letter (CLAS) number input value corresponding to various SIP memories. When designing the interface adapter board, it should be set according to this value, and ABUS will switch out the correct read and write timing.
The meaning of the seven-digit category indicating signal: T_XX_WW_CC, T is 1 for high and low test test, and 0 is for functional test at normal temperature. XX indicates the type of memory, WW indicates the bus width, and CC indicates the type of capacity.
Table 5 CLAS signal values ​​corresponding to various SIP memories
8-bit SRAM/MRAM/NOR FLASH interface IP core design
As shown in Figure 4-1, the interface operations of SRAM, MRAM and NOR FLASH are basically the same, and the bus timing of NIOSII is completely satisfied. Therefore, it is only necessary to simply connect the corresponding control lines and data lines in the FPGA. Only a chip select register is designed to distinguish 16 chip selects of the memory chip. The space that each chip select can access is 128MByte. The address of the chip select register is (base address +0 x0FFFFFFC), and the base address is set to the highest address of the NIOSII external bus.
Figure 4â€1 8-bit SRAM/MRAM/NOR FLASH Interface IP
16-bit SRAM/MRAM/NOR FLASH interface IP core design
As shown in Figure 4-2, the interface operations of SRAM, MRAM and NOR FLASH are basically the same, and the bus timing of NIOSII is completely satisfied. Therefore, it is only necessary to simply connect the corresponding control lines and data lines in the FPGA, but only design a chip select register to distinguish 16 chips of SIP. The space that each chip select can access is 128MByte. The address of the chip select register is (base address +0 x0FFFFFFC), and the base address is set to the highest address of the NIOSII external bus.
Figure 4â€2 16-bit SRAM/MRAM/NOR FLASH Interface IP
32-bit SRAM/MRAM/NOR FLASH interface IP core design
As shown in Figure 4-3, the interface operations of SRAM, MRAM, and NOR FLASH are basically the same, and the bus timing of NIOSII is completely satisfied. Therefore, it is only necessary to simply connect the corresponding control lines and data lines in the FPGA, but only design a chip select register to distinguish 16 chips of SIP. The space that each chip select can access is 128MByte. The address of the chip select register is (base address +0 x0FFFFFFC), and the base is set to the highest address of the NIOSII external bus.
Figure 4â€3 32-bit SRAM/MRAM/NOR FLASH Interface IP
40-bit SRAM/MRAM/NOR FLASH interface IP core design
As shown in Figure 4-4, the 40-bit data width is a bit special. Here we divide the 40-bit data into five 8-bit regions and use an 8-bit wide bus to access each region separately. The bit select register in the IP core is used to complete one of the five areas for switching the 8-bit data bus to the 40-bit bus. The address of the chip select register is (base address +0 x0FFFFFFC), and the address of the bit select register is (base address +0 x0FFFFFF8). Up to 128M × 40 bits × 16 slices of memory SRAM / MRAM / NOR FLASH module can be tested.
Figure 4â€4 40-bit SRAM/MRAM/NOR FLASH Interface IP
8-bit NAND FLASH ABUS interface IP design
As shown in Figure 4-5, one of the 16 chip selects of the module is selected by writing a chip select register. We agree that its address is (base address +0 x0FFFFFFC). The read status register returns the busy signal of 16 NAND FLASH chips, and its address is (base address +0 x0FFFFFF8). Writing data to the address (base address +0 x00) is a write to the NAND FLASH data register. Reading data to the address (base address +0 x00) unit is a read operation of the NAND FLASH data register. Writing data to the address (base address +0 x01) is a write to the NAND FLASH command register. Writing data to the address (base address +0 x02) is a write to the NAND FLASH address register.
Figure 4â€5 IP core design of ABUS interface for 8-bit NAND FLASH
16-bit NAND FLASH ABUS interface IP design
The 16-bit NAND FLASH memory chip can be combined in multiple ways, and can be combined with multiple 16-bit NAND FLASH or multiple 8-bit NAND FLASH. Here we assume that the 16-bit SIP NAND FLASH product is a combination of multiple 16-bit NAND FLASH. The following IP core is designed according to its structure.
As shown in Figure 4-6, one of the 16 chip selects of the module is selected by writing a chip select register. We agree that its address is (base address +0 x0FFFFFFC). read
The status register returns the busy signal of 16 NAND FLASH chips, and its address is (base address +0 x0FFFFFF8). Writing data to the address (base address +0 x00) is a write to the NAND FLASH data register. Reading data to the address (base address +0 x00) unit is a read operation of the NAND FLASH data register. Writing data to the address (base address +0 x01) is a write to the NAND FLASH command register. Writing data to the address (base address +0 x02) is a write to the NAND FLASH address register.
Figure 4â€6 IP Core Design of 16-Bit NAND FLASH ABUS Interface
Verification and summary
After writing the written FPGA program and the debugged C code to the FLASH, the FPGA is powered down and reconfigured. The output of the serial port can normally identify all the set memory chips and can perform accurate read and write function tests. Achieved the design purpose.
This paper introduces a low-cost, simple and flexible hardware design of a variety of memory chip test systems, and uses FPGA, FLASH, SDRAM, RS232 circuits and so on. With this solution, users can flexibly increase test system functions according to market demand and achieve more memory chip testing.
references:
[1]K9F4G08U0B 512M x 8 Bit / 1G x 8 Bit NAND Flash Memory datasheet, May 30, 2008
[2] Avalon Interface Specifications, Version 1.3, August 2010
[3] R1RP0416D Series 4M High Speed ​​SRAM datasheet, Rev. 1.00, Mar.12.2004
[4] HN58V1001 Series 1M EEPROM datasheet, Rev.7.0, Oct.31.1997
[5] MR0A08B 128K x 8 MRAM Memory datasheet, Rev.2, 6/2009
[6]S29JL064H 64 Megabit (8 M x ​​8-Bit/4 M x 16-Bit) datasheet, Revision A, March 26, 2004
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