1 Introduction
The MCS-51's memory has three channels: on-chip RAM, off-chip RAM, and ROM.
MCS-51 microcontroller has four storage spaces in physical structure
1, on-chip program memory (on-chip ROM)
2, off-chip program memory (off-chip ROM)
3, on-chip data memory (on-chip RAM)
4, off-chip data memory (off-chip RAM)
Logically (ie from the user's point of view) the MCS-51 microcontroller has three storage spaces.
1. 64K program memory (ROM) address space (MOVC) uniformly addressed inside and outside the chip
2, 256B on-chip data memory (on-chip RAM) address space (MOV)
3. Address space of 64K off-chip data memory (off-chip RAM) (MOVX)
Note: When accessing three different logical spaces, different forms of instructions should be used to generate strobe signals for different memory spaces.
2. Storage space division
2.1 On-chip RAM
Figure: On-chip AM address space division
The address range is 00H to 7FH (52 series extended to FFH), which is an 8-bit address, so the maximum addressable range is 256 unit addresses.
• 00H to 1FH
A total of 32 bytes, divided into four working register areas, each area has registers R0 ~ R7. For this area, you can use R0~R7 to operate, the code is short, but only one current workspace can be read and written. For this area, you can also use the byte address to read and write.
• 20H-2FH
A total of 16 bytes, is a bit addressing area, a total of 128 "bits", bit address: 00 ~ 7FH. This area can also be read and written by byte addressing.
• 30H-7FH
Nothing special, only byte addressing.
• 80H-FFH
There are 128 address numbers, of which 21 special function registers are discretely distributed, which must be directly addressed to read and write. (52 series, in this range, there is 128 bytes of RAM, which must be indirectly addressed to read and write).
Note: For reading and writing to the above space, the MOV instruction must be used.
2.2 off-chip RAM
The off-chip RAM address range is 0000H to FFFFH, and the capacity is 64KB. For reading and writing off-chip RAM, the MOVX instruction must be used.
Indirect addressing mode is adopted for off-chip RAM. R0, R1 and DPTR can be used as indirect addressing registers. R0 and R1 are 8-bit registers, that is, the addressing range of R0 and R1 is up to 256 units, and DPTR is 16-bit address pointer, the address range can reach 64KB.
That is to say, when addressing the off-chip RAM, the addressing range exceeds 256B, and R0 and R1 cannot be used as the indirect addressing registers, and the DPTR register must be used as the indirect addressing register.
2.3 ROM
The address range of the ROM is 0000H to FFFFH, the capacity is 64KB, and the address length is 16 bits. It is used to store the constants required for the program and program running.
Among them, 0000~0FFFH, that is, 4K, is on the chip, and the others are off-chip.
EA = 1, addressing the internal ROM; EA = 0, addressing the external ROM to ROM read, must use the MOVC instruction.
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