Foshan, Guangdong, August 22, 2017, Guangdong Gaoyun Semiconductor Technology Co., Ltd. (hereinafter referred to as “Gaoyun Semiconductorâ€) announced today that it supports both the non-volatile bee® family GW1N series and the medium density Chenxi® family GW2A. A family of LVDS gearbox interface IP cores (Gowin Generic LVDS Gearbox IP), including complete solutions for soft cores, reference designs and development boards.
Gaoyun GMDS gearbox interface IP realizes the switching between clock frequency and data bit width between internal logic and external interface, and ensures data throughput conservation, while supporting transmission function and receiving function, all cloud FPGA chip transceiver transmission The ratios support 1:1, 1:2, 1:4, 1:7, 1:8, and 1:10. In addition, the GW1N-6/9 devices also support a 1:16 switching ratio. For the different needs of the channel clock and the accompanying data phase relationship, the high cloud universal LVDS gearbox interface supports both edge alignment and intermediate alignment.
The high-cloud FPGA chip provides a dedicated unit module for building a high-speed LVDS interface that integrates unit modules and works together to achieve the corresponding functions based on customer-specific bandwidth, alignment, transceiver functions, and switching ratio requirements.
· High-speed, low-skew clock HCLK is used to support I/O for high-performance data transmission;
· GCLK is the internal system clock and the internal system clock must use the global clock network;
· A high-speed clock divider module that generates a divided clock GCLK that is in phase with the input clock HCLK;
· Phase-locked loop module realizes multiplication, frequency division and phase shift of the clock;
· Serial to parallel receiving side module for gearbox function;
· Parallel to serial transmit side module for gearbox function;
· Each I/O includes a delay module that provides a total delay of approximately 128 steps x 25 ps = 3200 ps.
"Gaoyun Universal LVDS gearbox interface IP makes full use of the various dedicated unit modules embedded in the high-cloud FPGA chip, enabling the high-speed FPGA device LVDS I/O interface speed to reach 800Mbps to 1.2Gbps performance requirements." Gao Yun Product Application Manager Mr. Xu Cai explained, "TCON market application, through the FPGA to control the timing action of the LCD screen, convert the input video signal such as LVDS signal into a form used by the data driving circuit such as Mini-LVDS or RSDS signal, and pass it to the data driving circuit. The control data driver circuit is turned on at the right time. The high-cloud FPGA chip is in line with the TCON market demand in terms of LVDS differential pin count and LVDS interface performance."
"Video acquisition and display technology is developing rapidly. Various video interfaces based on high-speed LVDS interface technology, such as Mini-LVDS, MIPI CSI-2/DSI, etc., are now widely used in mobile phones, tablets, VR, and unmanned. In applications such as mobile phones, in-vehicle entertainment systems, and human-machine interfaces (HMIs), there is an increasing demand for bridging and image processing of video interfaces in user systems.†Gao Yun Semiconductor Market Vice President and China Sales Director Huang Mr. Jun said, "Gaoyun Semiconductor has introduced a universal LVDS gearbox interface solution that combines the advantages of high-power semiconductor FPGA chips in non-volatile, small-thin packages, embedded high-capacity SDRAM, etc., for consumer and automotive electronics. Users in the industrial display market offer solutions for video interface bridging and image processing to help users speed time to market."
IP main feature IP working frequency· The LVDS I/O data rate is currently 1.2Gbps; the internal fabric clock rate is 120MHz for the GW1N series and 200MHz for the GW2A series.
TCON system architecture and IP callsThe video image data is converted into a parallel video signal by the LVDS 7:1 receiving module, and converted into the image format required by the LCD screen by the image processing module, and then converted into a mini-LVDS signal transmission by using the mini-LVDS 4:1 transmitting module. To the LCD screen.
GW1N/1NR, GW2A/2AR series FPGA chip
GW1N/1NR and GW2A/2AR series FPGA chips support various differential level standards such as LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVCECLE, and RSDSE. The I/O logic integrates multiple gear ratios for the switching ratio.
Development board and reference designGaoyun GMDS gearbox interface IP, reference design and development board support GW1N-4K FQPF144 package FPGA chip for LVDS receive signal and mini-LVDS transmit signal, subsequent upgrades will support GW2A series FPGA chip, further enhance LVDS I/O Interface performance.
Guangdong Gaoyun Semiconductor Technology Co., Ltd. was established in January 2014. The company is committed to developing domestic FPGA solutions and promoting its industrialization. It aims to launch a national brand FPGA chip with core independent intellectual property rights. The company aims to provide users with the highest quality service, and can provide one-stop services including chips, design software, soft core, reference design, and demonstration board.
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