Video technology of ultra high definition (UHD) H.264 video codec IP design

The H.264 codec IP, which includes the AL-H264E-4KI422-HW encoder and the AL-H264D-4KI422-HW decoder, developed by Atria Logic, has been successfully implemented on the Xilinx Zynq Z-7045 SoC. This integration enables high-quality UHD 4K video streaming at 60 frames per second. The system architecture is illustrated in the following figure:

A detailed block diagram of the H.264 codec IP designed by Atria Logic is shown below.

The AL-H264E-4KI422-HW encoder is a hardware-based IP core that offers low latency, high quality, and support for UHD Hi422 intra-frame encoding. It is paired with the AL-H264D-4KI422-HW low-latency decoder to ensure seamless video processing. The IP features include: - Comprehensive modular design for user customization and scalability - Support for intra-frame H.264 and Hi422 5.1 encoding and decoding - Integrated HDMI 2.0 receiving and transmitting subsystem - Compatibility with 8/10-bit video streams - Support for RGB and YUV 4:2:2/4:4:4 color formats - Ultra-low latency of approximately 0.3 seconds - Variable Bit Rate (VBR) and Constant Bit Rate (CBR) modes - High video quality with SSIM above 0.99% or PSNR over 50dB - Pre/post-processing capabilities including color space conversion, scaling, and subsampling - Gbps Ethernet output support To evaluate the performance of our UHD encoding and decoding IP cores, we needed a flexible and powerful platform. After careful consideration, we selected the Xilinx ZC706 evaluation kit, based on the Zynq Z-7045 SoC, due to the following advantages: - Availability of a ready-made FMC expansion board with a 4K HDMI interface (TB-FMC-HDMI 4K 2.0 daughter card) - Rich programmable logic resources that can accommodate the encoder and decoder IP while meeting strict timing requirements - Integration of a dual-core ARM Cortex-A9 processor, allowing us to develop custom applications and GUI interfaces - Support for advanced video formats such as 10-bit Hi422 and YUV 4:2:2, ensuring high fidelity in medical imaging and other critical applications The H.264 encoder supports 3840x2160p30 encoding with Hi422 format, providing superior image clarity and color accuracy. Its macro-module pipeline architecture reduces frame rate delay to approximately 0.3 milliseconds, enabling real-time 4K@60fps encoding. The encoder utilizes only 78% of the Zynq Z-7045's programmable logic and DSP resources, and 55% of its RAM, leaving ample room for additional circuits. Similarly, the H.264 decoder supports Hi422 and YUV 4:2:2 formats, and employs a pipeline architecture to minimize delay. It uses 68% of the programmable logic, 35% of the DSP resources, and 45% of the RAM, allowing for further expansion. The HDMI subsystem consists of two main modules: the TX and RX subsystems, as shown below.

The HDMI transceiver (GTX) module handles serial-to-parallel and parallel-to-serial data conversion using the Zynq SoC’s high-speed GT transceiver as the physical layer. The TX subsystem includes a transmission module, AXI Video conversion, timing control, and optional HDCP support. The RX subsystem processes incoming video and audio streams through AXI interfaces. The CPU interface allows the ARM Cortex-A9 processor to manage the HDMI subsystem efficiently, making this solution ideal for real-time video applications requiring minimal latency.

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