The latch is level triggered, the register is edge triggered, the register is triggered by the same clock edge, which conforms to the design idea of ​​the synchronous circuit, and the latch belongs to the asynchronous circuit design, which often leads to difficulty in timing analysis, and the improper application latch will be a large number. Waste chip resources.
Q37: Using a D flip-flop to make a two-way circuit? Draw a logic circuit? Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
enTIty two_de_fre is
Port(clk: in std_logic;
Reset: in std_logic;
Clk_out: out std_logic) ;
End two_de_fre;
Architecture Behavioral of two_de_fre is
Signal sig_clk: std_logic;
Begin
Process(clk)
Begin
If(reset = '1') then
Sig_clk <= '0';
Elsif(clk'event and clk = '1') then
Sig_clk <= not sig_clk;
End if;
End process;
Clk_out <= sig_clk;
End behavioral;
Display engineering design generally does not use this method to design, the two-way frequency is generally achieved by DCM. The divided signal obtained by DCM has no phase difference.
Q38: What is a state diagram?The state diagram is a geometrical representation of the state transition law of the sequential logic circuit and the relationship between the output and the input.
Q39: Design a 7-digit cyclic counter with preset value in the design method you are familiar with, which is 15? Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
enTIty seven_counter is
Port(reset:in std_logic;
Ck: in std_logic;
Counter_out std_logic_vector(2 downto 0));
End seven_counter;
Architecture Behavioral of seven_counter is
Signal sig_counter : std_logic_vector(2 downto 0);
Begin
Process(reset,clk)
Begin
If(reset = '1') then
Sig_count <= "101" ; -- initial value is 5
Elsif(clk'event and clk = '1') then
Sig_count <= sig_count + 1;
End if;
End process;
Counter_out <= sig_counter;
End behavioral;
The 15-ary counter design only needs to change counter_out and sig_counter to 4 digits;
Q39: Write a piece of code with VERILOG or VHDL to eliminate a glitch?The glitch can be eliminated by passing the transmitted signal through a two-stage trigger. (This is the way I use myself: this way to eliminate burrs is a condition that needs to be met, and there is no guarantee that it will be eliminated)
Q40: What is the difference between sram, falsh memory, and dram?Sram: Static random access memory, fast access speed, but small capacity, data loss after power failure, unlike DRAM requires constant REFRESH, high manufacturing cost, usually used as cache (CACHE) memory
Flash: flash memory, slow access speed, large capacity, data will not be lost after power failure
Dram: Dynamic random access memory, must constantly re-enhance (REFRESHED) potential difference, otherwise the potential difference will be reduced to not have enough energy to show what state each memory unit is in. The price is cheaper than sram, but the access speed is slower, the power consumption is larger, and it is often used as the memory of the computer.
Q41: There are four multiplexing modes, frequency division multiplexing, and writing the other three?Four multiplexing methods: Frequency Division Multiplexing (FDMA), Time Division Multiplexing (TDMA), Code Division Multiplexing (CDMA), Wavelength Division Multiplexing (WDM)
Q42: Give a combinational logic circuit that requires analysis of logic functions. The so-called combinatorial logic analysis is to find out the relationship between the output and input of a given logic circuit and to indicate the logic function of the circuit.
The analysis process is generally carried out as follows:
1: According to the given logic circuit, starting from the input, the logical function expression of the output is derived step by step.
2: List the truth table according to the output function expression;
3: Use words to summarize the logic function of the circuit;
1 Reduce system clock frequency
2 with faster response FF
3 Introduce a synchronization mechanism to prevent metastable propagation (you can use the two-stage trigger described above).
4 Improve clock quality, fast clock signal with edge changes
Feedback is the input of the power in the output loop to the input loop in the circuit system.
The types of feedback are: voltage series negative feedback, current series negative feedback, voltage parallel negative feedback, current parallel negative feedback.
The advantages of negative feedback: reduce the gain sensitivity of the amplifier, change the input resistance and output resistance, improve the linear and nonlinear distortion of the amplifier, effectively expand the passband of the amplifier, and automatically adjust the function.
Characteristics of voltage negative feedback: The output voltage of the circuit tends to remain constant.
Characteristics of current negative feedback: The output current of the circuit tends to remain constant.
Passive filter: This circuit mainly consists of passive components R, L and C. Active filter: integrated op amp and R, C components, with no inductance, small size, light weight and so on.
The open-loop voltage gain and input impedance of the integrated op amp are high, and the output resistance is small. After the active filter circuit is formed, it also has a certain voltage amplification and buffering effect. However, the bandwidth of the integrated op amp is limited, so the operating frequency of the current active filter circuit is difficult to do very high.
OTP means one TIme program, one-time programming
MTP means mulTI time program, multi-programming
OTP (One Time Program) is a memory type of MCU
MCUs can be classified into MASK (mask) ROM, OTP (one-time programmable) ROM, FLASHROM, etc. according to their memory types.
MASKROM's MCU is cheap, but the program is solidified at the factory, suitable for applications with fixed procedures.
FALSHROM's MCU program can be erased repeatedly, with great flexibility, but at a higher price, suitable for price-insensitive applications or for development purposes;
OTP ROM's MCU price is between the first two, and has one-time programmable capability, suitable for applications that require both flexibility and low cost, especially for electronic products that require continuous refurbishment and require rapid mass production. .
First, you should confirm that the power supply voltage is normal. Use a voltmeter to measure the voltage between the ground pin and the power pin to see if it is a supply voltage, such as the usual 5V.
The next step is to check if the reset pin voltage is normal. Measure the voltage value of pressing the reset button and releasing the reset button separately to see if it is correct.
Then check if the crystal oscillator starts to vibrate. Generally, use an oscilloscope to see the waveform of the crystal oscillator pin. Note that the “X10†file of the oscilloscope probe should be used. Another way is to measure the level of the IO port in the reset state, press and hold the reset button, and then measure the voltage of the IO port (except the P0 port that is not connected to the external pull-up) to see if it is high level, if not high power. Ping, mostly because the crystal oscillator does not start.
Another point to note is that if you use on-chip ROM (in most cases, there is very little external ROM expansion), be sure to pull the EA pin high, otherwise the program will run. . Sometimes the emulator can be used, but it is not possible to burn into the film, often because the EA pin is not pulled high (of course, the crystal oscillator does not start for the same reason). After the above checks, it is generally possible to troubleshoot. If the system is unstable, it is sometimes caused by poor power supply filtering. Connecting a 0.1uF capacitor between the power supply pin and the ground pin of the microcontroller will improve. If the power supply does not have a filter capacitor, you need to connect a larger filter capacitor, such as 220uF. When the system is unstable, you can try to connect the capacitor (the closer to the chip, the better).
Q48: Give reg the setup, hold time, and find the delay range of the intermediate combinatorial logic.Delay < period - setup – hold
Q49: The clock period is T. The register-to-output time of the flip-flop D1 is up to T1max and the minimum is T1min. The combined logic circuit has a maximum delay of T2max and a minimum of T2min. Q, what condition should be met for the setup time T3 and hold time of trigger D2?T3setup>T+T2max, T3hold>T1min+T2min
Q50: What is the difference between blocking assignment and non-package assignment? Non-blocking assignment: The assignment statement in the block is assigned at the same time, which is generally used in the description of the sequential circuit.
Blocking assignment: The operation of the next sentence can be done after the assignment statement is completed. It is generally used in the combination logic description.
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