Using the addressable remote sensor data path (HART) protocol, process measurement and control devices can communicate via traditional 4-20mA current loops. This protocol uses frequency shift keying (FSK) at frequencies of 1200 Hz and 2200 Hz. Here, one 1200 Hz period represents a logic 1 and two 2200 Hz periods represent a logic 0. Since the average value of the FSK waveform is always 0, the analog 4-20mA signal is not affected.
Ideally, the FSK signal consists of two frequency sine waves superimposed on the DC measurement signal. However, the generation of successive FSK sine waves is a very complicated process. Therefore, in order to simplify the generation process of the HART signal waveform, the physical layer of the HART specification defines the parameter limit values, and the amplitude, shape and conversion rate of the standardized waveform must not exceed these parameter limit values. In this case, a trapezoidal waveform is very suitable for this application. Figure 1 shows its various limits.
Figure 1 The minimum and maximum values ​​of the trapezoidal HART current waveform
The HART transmitter shown in Figure 2 provides a simple and low-cost solution that generates a trapezoidal HART waveform and superimposes it on a variable DC level, ultimately converting the resulting output voltage into a current loop .
Figure 2 Low-cost HART transmitter
The HART FSK signal (often generated by the local microcontroller unit [MCU]) is applied to the input of the first NAND gate (G1). The second output of the MCU's general-purpose I / O port functions as an active high "ENABLE" signal. G1 controls the two remote NAND gates (G2 and G3), and their outputs are connected together through high-impedance voltage dividers R1 and R2.
The second voltage divider composed of R4 and R5 divides the 5V power supply into a reference voltage of VREF = VCC / 2, which is 2.5V. As long as "Activation" is low, the output of G2 is low and the output of G3 is high. Due to the high impedance load, the NAND output has a rail-to-rail function; when R1 = R2, the input voltage of A1 non-inverting input VIN is also 2.5V.
When "active" is high, the G2 and G3 outputs commutate each other, forming a small square wave under VIN that swings symmetrically around VREF. The peak-to-peak amplitude of VIN is:
VS is a positive 5V power supply, and R1 || R2 is the parallel combination of R1 and R2.
Insert the resistance value in Figure 2 into the equation to get the input voltage swing of VIN (PP) = 200Mv, which makes the VIN swing between 2.4V and 2.6V. When VIN rises to 2.6V, the output of A1 immediately reaches a positive saturation state, and charges C3 through R6 and R7. The actual HART voltage of C3 (VHART) rises linearly until it reaches 2.6V. At this time, the amplifier A1 quickly exits the saturation state and acts as a voltage follower, thereby keeping VHART at 2.6V. When VIN drops to 2.4V, the A1 output enters a negative saturation state, and discharges C3 through R6 and R7. After that, VHART drops linearly until it reaches 2.4V. At this time, A1 exits the saturation state and acts as a voltage follower again, keeping VHART at 2.4V.
The resulting trapezoidal waveform is equal to VIN in amplitude and swings symmetrically around VREF. Its conversion rate is calculated as follows:
Among them, VSAT is the positive or negative output saturation voltage of A1.
Since the AC current of VHART is smaller than VSAT, VHART can be approximated by its static level VREF. In addition, the rail-to-rail output capability of A1 combined with the high impedance of the R6 load can obtain output saturation levels of 5V and 0V. Assuming that R7 is much smaller than R6, the previous expression can be simplified to:
If we insert the values ​​of the R6 and C3 components in Figure 2 into the equation, the slew rate of the trapezoidal waveform results in ± 1.25 V / ms.
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